1. Field of the Invention
This invention relates generally to the testing of Flash memory devices, and more particularly, to a test method to screen endurance rejects. Even more particularly, this invention relates to an erasability test method for a device that allows for the erase of multiple sectors of the device simultaneously during the erasability test.
2. Discussion of the Related Art
The standard test method used for Flash memory devices includes testing at the wafer level and testing after each individual die has been packaged. The wafer level testing is commonly done at room temperature and is called wafer sort. The package level testing is done after the wafer has been sawed into single chips and after each chip that has passed the wafer sort has been encapsulated in a package, which is typically plastic. The package level testing is commonly called final test or class test and is done at an elevated temperature, usually at a temperature selected from the range of 70 to 135xc2x0 C. Once the package level or class test is complete the Flash memory devices that pass the class test are marked appropriately and shipped to a customer.
The wafer sort is used to remove or screen-out the chips that have a defect or defects that occur during the fabrication of the wafer. The wafer sort is used to ensure that only those chips that have a possibility of being shipped to a customer are encapsulated in a package. This is done to control the packaging cost since bad chips are not packaged.
Presently, the class testing, also known as backend testing, is still necessary since the wafer sort is done at room temperature and some of the chips are sensitive to operations at elevated temperatures. The operations that are most sensitive to elevated temperatures are speed sorting (a sort that determines the speed of the Flash memory device), programmability, and certain low level leakage current testing. Other tests that are conducted during the backend testing are dc parametric tests, ac functionality and erasability. After the erasability tests are conducted, the dc parametrics and ac functionality are rechecked. Of course, a part of the backend testing is to ensure that the encapsulation (packaging) process did not damage the die.
A programming operation changes the logic state of a cell from a xe2x80x9c1xe2x80x9d (called xe2x80x9cblankxe2x80x9d) to a logic xe2x80x9c0xe2x80x9d (called xe2x80x9cprogrammedxe2x80x9d). A read operation detects the state of the cell, that is, whether the cell is in a blank state or in a programmed state. The programming and read operations are done at the byte level and/or word level, that is 8 cells (bits) at a time, and/or 16 cells (bits) at a time, on a Flash memory device. The erase operation is an operation that changes the state of a cell to a xe2x80x9c1xe2x80x9d or blank state. The erase operation is done on all cells in the array or sector of an array at the same time. To prevent xe2x80x9cover-erasurexe2x80x9d of an individual cell, all cells must be programmed to a logic xe2x80x9c0xe2x80x9d before the erase operation. Overerasure of a cell can cause problems during subsequent programming and read operations and in some cases would prevent the cell from being programmed. The typical Flash memory device must have all cells at a logic xe2x80x9c1xe2x80x9d when transferred to the class testing or when shipped to a customer. This means that if any cell is read as programmed, that is, read at a logic xe2x80x9c0xe2x80x9d then all cells must be programmed to a logic xe2x80x9c0xe2x80x9d, read, erased, and reread to ensure all cells are blank, that is, are at a logic xe2x80x9c1xe2x80x9d.
One of the problems encountered in the Flash memory art is that the cells are not exactly the same, that is, some cells either program or erase faster or slower than other cells. It is necessary, therefore, to provide a series of programming pulses or erase pulses to a device to ensure that all cells have substantially the same amount of charge (or lack of charge) on the floating gate. The key to a good device is that all cells in the device can be programmed or erased by being subjected to a series of program pulses or erase pulses with the number of pulses being within an acceptable range.
The wafer sort and backend (class) tests require lengthy test sequences due to the large number of memory cells that need to be read, programmed, read again, erased, and read again. The number of cells in a Flash memory device commonly exceeds 1-2 million cells and it is expected that this number will continue to increase.
Presently the art of production test methods for testing involve the usage of Sector Erase (SE) to screen out endurance related rejects and is based upon what a typical customer would do. Through monitoring the amount of time used during preprogramming, erase, and compensating for slightly overerased cells at a predetermined voltage in the SE mode, units that exceed predetermined time limits are rejected in volume production testing. Those units that are programmed or erased within the predetermined time limits are considered saleable to customers. The method of determining the time limits is by an initial characterization of the device. The SE method of screening endurance-related rejects utilizes a mode wherein the erasability testing is limited to a single sector of the Flash memory device at a time. Being limited to testing a single sector at a time extends the testing time and represents a substantial portion of the costs associated with the manufacturing of Flash memory devices. In order to remain competitive, flash memory device manufacturers must decrease the cost of manufacturing in any way possible.
Therefore, what is needed is a method of testing that decreases the time needed to accurately screen endurance-related rejects in Flash memory devices utilizing a mode wherein multiple sectors in the Flash memory device can be tested simultaneously.
According to the present invention, the foregoing and other objects and advantages are attained by a method of utilizing Fast Chip Erase to screen endurance rejects during testing of a Flash memory device. Multiple sectors of the Flash memory device are selected and it is determined if all the cells in the multiple sectors are programmed. If all the cells in the multiple sectors are not programmed, the unprogrammed cells are programmed and the time to complete this operation is monitored and if the time exceeds a first predetermined time the testing is terminated.
In accordance with an aspect of the invention, all the cells in the multiple sectors are erased and the time necessary to erase all the cells without having any overerased cells is monitored and if the time exceeds a second predetermined time the testing is terminated.
In accordance with another aspect of the invention, overerased cells in the multiple sectors are corrected when they are detected and the time to correct for overerased cells is monitored and if the time exceeds a third predetermined time the testing is terminated.
In accordance with still another aspect of the invention, the total time after the application of erase pulses to the cells until the cells are overerase corrected is monitored and if this time exceeds a fourth predetermined time the testing is terminated.
In accordance with another aspect of the invention, the testing on the multiple sectors is finished when all the cells are erased and the total time for determining the erasability of the Flash memory device is monitored and if this time exceeds a fifth predetermined time, the testing is terminated.
In accordance with another aspect of the invention, this procedure repeats until all sectors in the Flash memory device have been tested.
In accordance with another aspect of the invention, the first through the fifth predetermined times are determined during an initial characterization of the Flash memory device.
The described method of utilizing Fast Chip Erase to screen endurance rejects during testing of a Flash memory device thus provides an accurate method to test multiple sectors of the Flash memory device simultaneously and thereby decreases total testing time. This results in substantial savings in manufacturing and testing costs.
The present invention is better understood upon consideration of the detailed description below, in conjunction with the accompanying drawings. As will become readily apparent to those skilled in the art from the following description, there is shown and an embodiment of this invention simply by way of illustration of the best mode to carry out the invention. As will be realized, the invention is capable of other embodiments and its several details are capable of modifications in various obvious aspects, all without departing from the scope of the invention. Accordingly, the drawings and detailed description will be regarded as illustrative in nature and not as restrictive.